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AS8650 high-efficient power management device with high-speed can interface www.austriamicrosystems.com/AS8650 revision 1.0 1 - 46 datasheet 1 general description the AS8650 is a companion ic which combines power management functions and a fully conforming high speed can transceiver in one high performance analog device for automotive applications. the AS8650 is powered by the battery, provides 4 output voltage levels of which 3 outputs can be individually programmed in the range of 1.8v to 3.3v with a maximum current consumption up to 120ma at the ldo voltage regulator outputs. an integrated dcdc converter with a very high efficiency for the 5v output supplies the 3 voltage regulators and ensures a voltage stability of 2.5%. the combination of dcdc converter with low-drop-out voltage regulators makes the AS8650 suitable for all automotive control units where power efficiency is a must. the AS8650 provides a high-speed can interface up to 1mbps communication rate conforming to iso 11898. the AS8650 provides wake-up via remote wake-up at can bus lines and a local wake pin. the watchdog unit provides three different timing functions: start-up, window- and time-out watchdog; configurable via the spi and i2c interface. voltage monitoring is implemented for the battery supply, dcdc output and the 3 ldo regulator outputs. undervoltage will be signalled on the intn pin to the microcontroller. all diagnostics and status flags can be accessed with the spi interface. the product is available in a 36-pin qfn (6x6x0.9) package. 2 key features dcdc converter for 5v output with very high efficiency 2 programmable voltage regulators in the range of 1.8v to 3.3v high-speed can interface (iso 11898) with remote wake-up comprehensive voltage monitoring configurable watchdog functions for start-up, operation, and standby automatic thermal shutdown protection excellent emc performance with outstanding switching technology for the dcdc converter ambient temperature range from -40c to +105c in maximum load conditions lead-free 36-pin qf n (6x6x0.9) package 3 applications the AS8650 provides high efficient and flexible power supply together with state-of-the-art high speed can interface for automotive control units.the device is pin compatible with as8550 (lin interface) in order to change from can to lin easy. dc / dc converter 5v i2c spi high-speed can transceiver watchdog cs spi sclk i2c /sclk spi i2c_en canh rxd txd reset fb configurable voltage regulator configurable voltage regulator configurable voltage regulator v reg digital logic intn wake v5v_ldo1 v5v_ldo2 v5v_ldo3 gnd vsup lx v reg v reg split canl sda i2c / sdi spi sdo spi AS8650 figure 1. AS8650 block diagram
www.austriamicrosystems.com/AS8650 revision 1.0 2 - 46 AS8650 datasheet - contents contents 1 general description ......................................................................................................... ......................................................... 1 2 key features................................................................................................................ ............................................................. 1 3 applications................................................................................................................ ............................................................... 1 4 pin assignments ............................................................................................................. .......................................................... 4 4.1 pin descriptions.......................................................................................................... .......................................................................... 4 5 absolute maximum ratings .................................................................................................... .................................................. 6 6 electrical characteristics.................................................................................................. ......................................................... 7 6.1 electrical system specification........................................................................................... .................................................................. 8 6.2 dcdc converter ............................................................................................................ ...................................................................... 8 6.3 low drop out regulators ................................................................................................... .................................................................. 9 6.4 can transceiver ........................................................................................................... ..................................................................... 10 6.4.1 timing diagrams......................................................................................................... ............................................................... 12 6.5 undervoltage detection .................................................................................................... .................................................................. 13 7 detailed description........................................................................................................ ........................................................ 14 7.1 operating modes and states................................................................................................ .............................................................. 14 7.1.1 normal mode ............................................................................................................. ................................................................ 14 7.1.2 receive-only mode ....................................................................................................... ............................................................. 14 7.1.3 standby mode............................................................................................................ ................................................................ 14 7.1.4 sleep mode.............................................................................................................. .................................................................. 14 7.2 power management strategy ................................................................................................. ............................................................ 14 7.3 state diagram............................................................................................................. ........................................................................ 17 7.4 initialization sequence................................................................................................... ..................................................................... 17 7.5 dcdc converter ............................................................................................................ .................................................................... 19 7.6 voltage regulator ldo1.................................................................................................... ................................................................. 19 7.7 voltage regulator ldo2.................................................................................................... ................................................................. 19 7.8 voltage regulator ldo3.................................................................................................... ................................................................. 19 7.9 over-temperature monitor .................................................................................................. ............................................................... 19 7.10 undervoltage reset....................................................................................................... ................................................................... 19 7.11 reset block............................................................................................................. ......................................................................... 20 7.12 can transceiver .......................................................................................................... .................................................................... 21 7.12.1 bus driver............................................................................................................. .................................................................. 21 7.12.2 normal receiver ........................................................................................................ .............................................................. 21 7.12.3 low power receiver..................................................................................................... ........................................................... 21 7.12.4 operating modes ........................................................................................................ ............................................................. 21 7.12.5 local wake-up event.................................................................................................... ........................................................... 21 7.12.6 remote wake-up......................................................................................................... ............................................................ 22 7.13 internal flags........................................................................................................... ......................................................................... 23 7.13.1 vsup_uv_flag ........................................................................................................... ............................................................. 23 7.13.2 vsup_pok_flag.......................................................................................................... ............................................................ 23 7.13.3 v5v_uv_flag ............................................................................................................ ............................................................... 23 7.13.4 v5v_pok_flag........................................................................................................... .............................................................. 23 7.13.5 vldo2_uv_flag .......................................................................................................... ............................................................ 23 7.13.6 vldo2_pok_flag......................................................................................................... ........................................................... 23 7.13.7 vldo3_uv_flag .......................................................................................................... ............................................................ 23 7.13.8 vldo3_pok_flag......................................................................................................... ........................................................... 23
www.austriamicrosystems.com/AS8650 revision 1.0 3 - 46 AS8650 datasheet - contents 7.13.9 bus wake_up flag ....................................................................................................... .......................................................... 23 7.13.10 local wake_up flag .................................................................................................... .......................................................... 24 7.13.11 ovt_warning flag ...................................................................................................... .......................................................... 24 7.13.12 ovt_recover flag ...................................................................................................... .......................................................... 24 7.13.13 bus failure flags..................................................................................................... .............................................................. 24 7.13.14 local failure flags ................................................................................................... ............................................................. 24 7.14 watchdog (wd) ............................................................................................................ .................................................................... 25 7.14.1 start-up watchdog behavior............................................................................................. ....................................................... 25 7.14.2 window watchdog behavior............................................................................................... ..................................................... 25 7.14.3 time-out watchdog behavior ............................................................................................. ..................................................... 26 7.15 interrupt generation ..................................................................................................... .................................................................... 26 7.16 status registers ......................................................................................................... ...................................................................... 27 8 application information ..................................................................................................... ...................................................... 28 8.1 serial peripheral interface ............................................................................................... ................................................................... 28 8.1.1 spi write operation..................................................................................................... .............................................................. 29 8.1.2 spi read operation...................................................................................................... ............................................................. 30 8.1.3 spi timing diagram...................................................................................................... ............................................................. 31 8.2 inter-integrated circuit (i2c) interface.................................................................................. .............................................................. 32 8.2.1 i2c write operation ..................................................................................................... .............................................................. 32 8.2.2 i2c read operation...................................................................................................... ............................................................. 33 8.3 digital timing specification .............................................................................................. .................................................................. 34 8.3.1 system specification and timings........................................................................................ ..................................................... 37 8.4 register space ............................................................................................................ ....................................................................... 38 9 package drawings and markings ............................................................................................... ............................................ 43 10 ordering information....................................................................................................... ...................................................... 45
www.austriamicrosystems.com/AS8650 revision 1.0 4 - 46 AS8650 datasheet - pin assignments 4 pin assignments figure 2. pin assignments (top view) 4.1 pin descriptions table 1. pin descriptions pin pin name pin type description 1, 2, 3 vsup power supply input power supply 4 gnd_dcdc 5gnd 6 wake analog input / output high-voltage local wake request (high-voltage input) 7canh high level can bus line 8canl low level can bus line 9 gnd_can power supply input power supply 10 split analog input / output high-voltage common-mode stabilization output wake canh canl vsup rxd sdo spi cs spi AS8650 txd 27 sclk i2c (sclk spi ) sda i2c / sdi spi 26 25 24 23 22 21 20 19 30 29 28 36 35 34 33 32 31 qfn 6x6x0.9 1 2 3 4 5 6 7 8 9 16 17 18 10 11 12 13 14 15 lx fb v5v_ldo2 vldo1 vldo2 vldo3 intn reset gnd (exposed pad) reserved reserved reserved vldo3fb split vsup vsup gnd_can lx lx v5v_ldo3 vldo2fb vldo1fb v5v_ldo1 gnd_dcdc gnd i2c_en
www.austriamicrosystems.com/AS8650 revision 1.0 5 - 46 AS8650 datasheet - pin assignments 11 i2c_en digital input i2c/spi select signal (high = i2c, low = spi) 12 sda i2c / sdi spi digital input/output / digital input unidirectional for spi, bidirectional for i2c 13 sdo spi digital output spi data out 14 sclk i2c / sclk spi digital input serial clock (multiplexed for i2c and spi) unidirectional 15 cs spi digital input with pull-up spi chip select 16 rxd digital output with pull-up can transceiver receive signal 17 intn digital output active low interrupt to c. generated if status/ diagnostic is updated. 18 txd digital input with pull-up can transceiver transmit signal 19 reset digital output digital output referenced to vldo1, active low 20 reserved pin with digital / analog input / open-drain-output reserved 21 analog input / output 22 23 vldo1 power supply input regulated voltage output 24 vldo1fb pin with digital / analog input / open-drain-output regulated voltage feedback 25 vldo2 power supply input regulated voltage output 26 vldo2fb pin with digital / analog input / open-drain-output regulated voltage feedback 27 vldo3fb regulated voltage feedback 28 vldo3 power supply input regulated voltage output 29 v5v_ldo1 step-down converter 5v output, supply for ldo1 30 v5v_ldo3 step-down converter 5v output, supply for ldo3 31 v5v_ldo2 step-down converter 5v output, supply for ldo2 32 fb (dcdc) analog input dcdc output voltage feedback 33, 34, 35 lx (dcdc) power supply input dcdc output 0gnd exposed pad (gnd) table 1. pin descriptions pin pin name pin type description
www.austriamicrosystems.com/AS8650 revision 1.0 6 - 46 AS8650 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions beyond those indicated in electrical characteristics on page 7 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings 1 1. all voltages mentioned above are referred with respect to ground reference voltage v gnd . parameter min max units notes electrical parameters voltage at positive supply pin (v vsup ) -0.3 40 v voltage at pin v5v_ldo1, v5v_ldo2, v5v_ldo3, vldo1, vldo2, vldo3, fb, vldo1fb, vldo2fb, vldo3fb -0.3 7 v voltage at pin canh, canl, split -40 +40 v voltage at pin lx, wake -0.3 v vsup + 0.3 v voltage at pin reset, intn, rxd, txd, cs, sclk, sdo, sda/sdi, i2c_en -0.3 4.5 v input supply slew-rate (v sup_slew ) 1 v/s input power supply ramp rate electrostatic discharge electrostatic discharge voltage aec-q100-002 human body model standard (esd) 2 kv all pins except vsup, gnd, canh, canl, wake, split 4 vsup, gnd, wake, split 8 canh, canl latch-up immunity -100 +100 ma aec-q100-004 continuous power dissipation maximum power dissipation (p tot ) 1.2 w temperature ranges and storage conditions junction temperature (t j )170oc storage temperature (t stg ) -50 +125 oc thermal resistance mlf package (r thj_36 ) 30 oc/w semi g42-88 package body temperature (t body )260oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/ jedec j-std-020 ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn). moisture sensitivity level 3 represents a maximum floor life time of 168h
www.austriamicrosystems.com/AS8650 revision 1.0 7 - 46 AS8650 datasheet - electrical characteristics 6 electrical characteristics table 3. electrical characteristics symbol parameter conditions min typ max units operating conditions v sup positive supply voltage normal operating condition 6 18 v gnd ground in reference to all the voltages 0 v t amb ambient temperature junction temperature (t j ) 150oc (at full-load) -40 105 oc i supp supply current, normal mode vsup = 6v, ldos at full load, dcdc load = 390ma, can dominant 425 ma vsup = 18v, ldos at full load, dcdc load = 390ma, can dominant, not production tested. 150 vsup = 16v, ldos at full load, can dominant 170 cs vt- negative-going threshold vldo1 = 3.3v 1.12 1.52 v vt+ positive-going threshold 1.77 2.23 v i lil_cs pull up current in cs pad, pulled up to vldo1 -60 -15 a sdo v oh high level output voltage 2.5 v v ol low level output voltage vsup 6v 0.4 v i o output drive current 4 ma sda / sdi v ih high level input voltage 0.7* vldo1 v v il low level input voltage 0.3* vldo1 v v ol low level output voltage 0.4 v sclk v ih high level input voltage open-drain, external 500 pull-up 0.7* vldo1 v v il low level input voltage 0.3* vldo1 v reset, intn v oh high level output voltage 2.5 v v ol low level output voltage vsup 6v 0.4 v i o output drive current 4 ma txd v ih high level input voltage 2.0 v v il low level input voltage 0.8 v i o output drive current vsup 6v 1 ma
www.austriamicrosystems.com/AS8650 revision 1.0 8 - 46 AS8650 datasheet - electrical characteristics 6.1 electrical syst em specification -40c < t j < 150c 6.2 dcdc converter -40c < t j < 150c; all voltages are with respect to ground, normal operating mode, unless otherwise mentioned . i lil pull-up current txd pulled up to vldo1 with control rxd pulled up to vldo1 -60 -15 a rxd v oh high level output voltage 2.5 v v ol low level output voltage 0.4 v i o output drive current vsup 6v 1 ma i lil pull-up current txd pulled up to vldo1 with control rxd pulled up to vldo1 -60 -15 a table 4. electrical system specification symbol parameter conditions min typ max units iddnom current consumption normal mode no load, vsup = 12v, can recessive 3.5 6 ma iddrecv current consumption receive-only mode no load, vsup = 12v, can recessive 1 2 ma iddstby current consumption standby mode no load, vsup = 12v 135 270 a iddsleep current consumption sleep mode no load, vsup = 12v 75 150 a table 5. dcdc converter symbol parameter conditions min typ max units vsup battery voltage range 6 12 18 v v5v output voltage for inductor 22h and capacitor 100f 4.75 5 5.25 v i lxs lx current limit 0.8 1 1.25 a i v5v dcdc output current 500 ma r on lx switch on-resistance (bondwire resistance included) 0.8 1 v fb reference voltage for fb 4.75 5 5.25 v lireg_dc line regulation step from v in = 6v to v in 2 = 18v, i load = 100ma lireg = 100*(v out 1-v out 2) / [v out 2*(v in 1-v in 2)] -0.1 +0.1 % / v loreg_dc load regulation i load step from 90ma to 10ma vsup = 12v loreg = 100*(v_90ma-v_10ma) / v_90ma -0.9 +0.9 % lx_ind output inductor 10 22 h v5v_cer1 output ceramic capacitor 1 10 100 f v5v_esr1 esr of ceramic capacitor 1 0 0.05 v5v_cer2 output ceramic capacitor 2 x7r type 100 220 nf v5v_esr2 esr of ceramic capacitor 2 0.01 csup input capacitor (ceramic) for emc suppression 22 100 f csup_esr 1 table 3. electrical characteristics symbol parameter conditions min typ max units
www.austriamicrosystems.com/AS8650 revision 1.0 9 - 46 AS8650 datasheet - electrical characteristics 6.3 low drop out regulators -40c < tj < 150c; all voltages are with respect to ground, normal operating mode, unless otherwise mentioned. the ldo block is a linear voltage regulator, which provides a regulated (band-gap stabilize d) output voltage from the dcdc converter output voltage (v5v) . table 6. vldo1 1 block specifications 1. please note that the vldo1 is not programmable. symbol parameter conditions min typ max units v5v input voltage range 4.75 5 5.25 v i outldo1 output current guaranteed by design. not production tested. 0 100 ma vldo1 output voltage range 3.217 3.3 3.383 v icc_sh output short circuit current normal mode 300 ma dvldo1 line regulation vldo1/ v5v (static) for the input range, i load = 100ma -8 8 mv/v loreg_nm load regulation vldo1 (for 100ma > i load > 1ma), v5v = 5v -0.15 +0.15 mv/ma t ldo start-up time guaranteed by design (includes start-up time of dcdc converter) 80 ms cl2 output capacitor (ceramic) x7r type 2 5 f esr2 0.02 0.1 cl1 x7r type 100 220 nf esr1 0.01 table 7. vldo2 1 block specifications 1. 3.3v to 1.8v output. symbol parameter conditions min typ max units v5v input voltage range 4.75 5 5.25 v ioutldo2 output current guaranteed by design. not production tested. 0120ma vldo2 output voltage range v out (typ) depends on the trim code as in otp register mapping. default code gives 2.8v 0.975* v out v out 1.025* v out v icc_sh output short circuit current normal mode 300 ma dvldo2 line regulation vldo2/ v5v (static) for the input range, i load = 100ma -8 8 mv/v loreg_nm load regulation vldo2 (for 120ma > i load > 1ma) -0.15 +0.15 mv/ma t ldo start-up time guaranteed by design (includes start-up time of dcdc converter) 80 ms cl2 output capacitor (ceramic) x7r type 2 5 f esr2 0.02 0.1 cl1 x7r type 100 220 nf esr1 0.01
www.austriamicrosystems.com/AS8650 revision 1.0 10 - 46 AS8650 datasheet - electrical characteristics 6.4 can transceiver 6v < vsup < 18v; -40c < tj < 150oc; all voltages are with respect to ground; 4.75v < v5v_ldo1 < 5.25v; rl=60 . table 8. vldo3 1 block specifications symbol parameter conditions min typ max units v5v input voltage range 4.75 5 5.25 v i outldo3 output current guaranteed by design. not production tested. 0 100 ma vldo3 output voltage range v out (typ) depends on the trim code as in otp register mapping. default code gives 1.8v 0.975* v out v out 1.025* v out v icc_sh output short circuit current normal mode 300 ma dvldo3 line regulation vldo3/ v5v (static) for the input range, i load = 100ma -8 8 mv/v loreg_nm load regulation vldo3 (for 100ma > i load > 1ma) -0.15 +0.15 mv/ma t ldo start-up time guaranteed by design (includes start-up time of dcdc converter) 80 ms cl2 output capacitor (ceramic) x7r type 2 5 f esr2 0.02 0.1 cl1 output capacitor (ceramic) x7r type 100 220 nf esr1 0.01 1. 3.3v to 1.8v output. table 9. dc electrical characteristics symbol parameter conditions min typ max units driver canh_dom dominant output voltage v_txd = 0v 34.25v canl_dom 0.5 1.75 v vo_dom_m matching dominant output voltage v5v_ldo1-v_canh-v_canl -0.1 0.15 v vo_diff differential output voltage v_canh-v_canl 45 < rl < 60 , v_txd = 0v (dominant) 1.5 3 v no load; v_txd = vldo1 (recessive) -50 50 mv vo_rec recessive output voltage v_canh, v_canl v_txd = vldo1; no bus load, normal mode 23v no bus load, stand-by mode -0.1 0.1 v io_short short circuit output current v_txd = 0v, v_canh = 0v -160 -50 ma v_txd = 0v, v_canl = 40v +50 +160 ma io_rec recessive output current -27v < v_can < 40v -2.5 +2.5 ma receiver v_rxd_th differential receiver threshold voltage -12v < v_canh < 12v -12v < v_canl < 12v receive only mode (can receiver) 0.5 0.9 v -12v < v_canh < 12v -12v < v_canl < 12v stand-by mode (low-power receiver) 0.4 1.15 v
www.austriamicrosystems.com/AS8650 revision 1.0 11 - 46 AS8650 datasheet - electrical characteristics v_rxd_hys differential receiver hysteresis voltage -12v < v_canh < 12v -12v < v_canl < 12v receive only mode (can receiver) 20 130 mv i_rxd_leak input leakage current v5v_ldo1 = 0v; v_canh = v_canl = 5v 100 250 a r_in_cm common mode input resistance tested in receive only mode 15 35 k r_in_cm_m common mode input resistance matching v_canh = v_canl (tested in receive only mode) -3 +3 % r_in_diff differential input resistance tested in receive only mode 25 75 k vo_split output voltage on split pin normal mode -500a < i_split < 500a 0.3* v5v_ldo1 0.7* v5v_ldo1 v il_split leakage current on split pin stand-by mode 0v < v_split < 35v (not production tested) -5 +5 a stand-by mode -22v < v_split < 0 (not production tested) -1 +1 ma table 10. ac electrical characteristics symbol parameter conditions min typ max units t_txd_bus_on delay txd to bus dominant 10 110 ns t_txd_bus_off delay txd to bus recessive 10 140 ns t_bus_on_rxd delay bus dominant to rxd 15 115 ns t_bus_off_rxd delay bus recessive to rxd 20 160 ns t_txd_rxd propagation delay txd to rxd 40 255 ns wake up via bus t_bus_wr dominant time for wake-up detection via bus 0.75 5 s bus diagnostic t_oc_canh time to detect over current canh v_txd = 0v, v_canh = 0v (not production tested) 60 s t_lc_canh time to detect low current canh v_txd = 0v, v_canh = 40v (not production tested) 60 s t_oc_canl time to detect over current canl v_txd = 0v, v_canl = 40v (not production tested) 60 s t_lc_canl time to detect low current canl v_txd = 0v, v_canl = 0v (not production tested) 60 s table 11. temperature limiter symbol parameter conditions min typ max units t jshut shut down temperature junction temper ature when ic shuts down 150 170 185 oc t jrecv recovery temperature junction temperature below which state machine returns from shutdown/warning 125 140 155 oc t jwarn over-temperature warning flag set junction temperature beyond which the warning flag is set 140 157 175 oc table 9. dc electrical characteristics symbol parameter conditions min typ max units
www.austriamicrosystems.com/AS8650 revision 1.0 12 - 46 AS8650 datasheet - electrical characteristics 6.4.1 timing diagrams figure 3. timing diagram and hysteresis of can receiver txd canh_dom canl_dom vo_rec vin_diff rxd 2.5v 0.4v 0.9v 0.5v t_txd_bus_on t_txd_bus_off t_bus_on_rxd t_bus_off_rxd t_txd_rxd t_txd_rxd v_rxd v_rxd_th (high) v_rxd_th (low) v_rxd_hys vin_diff
www.austriamicrosystems.com/AS8650 revision 1.0 13 - 46 AS8650 datasheet - electrical characteristics 6.5 undervoltage detection table 12. undervoltage detection symbol parameter conditions min typ max units vsup_por vsup power on reset threshold on rising edge of vsup 5.09 5.5 5.91 v vsup_reset vsup power on reset threshold off (master reset for device) 4.49 4.85 5.21 v vsup_pokth vsup undervoltage threshold off vsup rising edge. (brown out reset threshold) 4.95 5.35 5.75 v vsup_uvth vsup undervoltage threshold on (can bus in recessive state) vsup falling edge. (brown out reset threshold) 4.625 5.0 5.375 v v5v_pokth v5v undervoltage threshold off rising edge of v5v 4.16 4.5 4.84 v v5v_uvth v5v undervoltage threshold on falling edge of v5v 3.8 4.1 4.4 v vldo_pokth ldo undervoltage threshold off (vldo1, vldo2 and vldo3) percent value is with respect to ldo output. rising edge of ldo 87 89 91 % vldo_uvth ldo undervoltage threshold on (vldo1, vldo2 and vldo3) percent value is with respect to ldo output. falling edge of ldo 78 80 82 % t rr spike filter on vldo1 to remove disturbance 2 4 8 s t res reset delay time 4812ms
www.austriamicrosystems.com/AS8650 revision 1.0 14 - 46 AS8650 datasheet - detailed description 7 detailed description the AS8650 consists of the following components on chip: dcdc converter with 5v outputs that supplies the three ldo voltage regulators and the can transceiver one voltage regulator for 3.3v output voltage and two programmable voltage regulators in the range of 3.3v to 1.8v can bus transceiver according to iso 11898 integrated reset unit with a power-on-reset delay and a programmable watchdog time 7.1 operating modes and states the AS8650 provides four main operating modes normal, receive only, standby, and sleep. in normal mode, the can transceiver can be disabled in case of over-temperature condition. the detailed transition table for each mode is shown in the subsequent pages. 7.1.1 normal mode in normal mode dcdc converter, the three voltage regulators, bus transceiver, and window watchdog are turned on with full funct ionality. all the ldo regulators are capable of delivering maximum load current possible as per their respective ratings. the bus transceiver is capable of sending the txd data from the microcontroller to the canh at the maximum rate. 7.1.2 receive-only mode in this mode, the can transmitter is disabled. the can receiver, the three voltage regulators, and over-temperature monitor cir cuit are enabled. 7.1.3 standby mode this is the mode after power up. the standby mode is a functional low-power mode where the can transceiver is disabled. the bus wake-up (low power receiver) circuit, ldo1, and over-temperature monitor circuit are enabled. both ldo2 and ldo3 can be enabled or disa bled (default state) using the host command. the AS8650 can enter normal mode, sleep mode or receive only mode through host command. 7.1.4 sleep mode sleep mode is the current saving mode that is entered by host command or by over-temperature condition. the dcdc converter, the three voltage regulators, can transceiver, the reset, and window watchdog unit are all switched off. the bus wake-up (low power recei ver) circuit, oscillator, and over-temperature monitor circuit are active. the bus is in recessive state (high). the only wake-up possible is through remote wake-up (through the bus li nes) or local wake up (thr ough the wake pin) as desc ribed in the wake specific ation. in the case of entering sleep mode due to over-temperature condition (t > t jshut ), the device can come out of sleep only after the temperature falls back below the return temperature t jrecv and any one of the wake up events mentioned above. 7.2 power management strategy the detailed block diagram and the power management strategy are shown in figure 4 . internal regulator. this module is powered externally by the vsup. all the critical modules that needs to be kept always on, work on this supply. some of the important modules among them are over-temperature monitor, local wake block, internal power-on reset module , internal oscillator, complete mode-control unit, undervoltage comparators of three external ldos. dcdc converter. this is the main supply regulator for all the internal blocks. a step-down hysteretic buck converter is used to generate 5v output from vsup. this 5v output is then used to generate all the three ldos. this high-efficiency step-down dcdc converter con tains the following features: current limited operation thermal shutdown ldo1. this is the main i/o supply. this is generated internally from the 5v dcdc converter output and gives a regulated 3.3v output t o power- up the external micro-controller. all the i/os that interface with the micro-controller work on this supply. ldo2 and ldo3. these are two regulators that are generated from the 5v dcdc converter output. both the ldos can be programmed via i2c or spi settings in the range from 3.3v to 1.8v.
www.austriamicrosystems.com/AS8650 revision 1.0 15 - 46 AS8650 datasheet - detailed description figure 4. power management strategy mode control / reset generation digital interface window watchdog ldo1 (100ma) ldo2 (120ma) ldo3 (100ma) uv comp uv comp uv comp otp level shifter definer level shifter definer definer definer level shifter por clk osc_en start done level shifter definer lx v5v v3p3 v2p8 v1p8 level shifter reset intn txd rxd cs spi sclk i2c / sclk spi sda i2c / sdi spi sdo spi ldo1_en ldo2_en ldo3_en local wake otm wake canh canl split ldo1_uvb ldo2_uvb ldo3_uvb tx_en tx rx_en rx flags otm_160 otm_170 otm_en loc_wake vsup gnd fb ldo1 pre-reg dcdc 5v definer i2c_en osc pre-reg 3.3v & 5.0v dcdc converter 5v por can transceiver
www.austriamicrosystems.com/AS8650 revision 1.0 16 - 46 AS8650 datasheet - detailed description table 13. power management strategy for AS8650 control states power-up normal rx only standby sleep analog blocks dcdc converter on on on on off 1 1. can be turned on using device configuration register oscillator on on on on on internal regulator on on on on on otm on on ononon ldo1 on on on on off ldo2 off on 2 2. can be turned off using device configuration register on 2 off 1 off ldo3 off on 2 on 2 off 1 off can tx off on off off off can rx off on on off off low power rx off off off on on local wake off off off on on split generation off on on on on digital blocks wwd off on on on off digital interface off on on on off
www.austriamicrosystems.com/AS8650 revision 1.0 17 - 46 AS8650 datasheet - detailed description 7.3 state diagram figure 5. state machine model 7.4 initialization sequence after this, dcdc converter is switched on, on receiving pg (power good) signal from dcdc converter, ldo1 regulator is switched on. if vldo1 > vldo1_pokth threshold, vldo1_reset is generated. after this, active-low porn _2_otp is generated . the rising edge of porn_2_otp loads contents of fuse onto the otp latch after load access time t load . the load_otp_in_prereg signal loads the content of otp latch into the pre-re gulator domain register. the reset timeout is also started. the reset signa l is de-asserted after rese t timeout period t res . after the reset is high, startup watch dog will start. if microcontrolle r gives trigger within star tup window th e device enters into standby mode. if microcontro ller misses the trigger, reset signa l is generated and again reset timeou t will start. if microcontroller m isses to give the startup watchdog trigger for 3 consecutive times, then the device enters into sleep mode. on receiving normal mode command from microcontroller, device turns on the ldo2 and ldo3 regulators. when vldo2 and vldo3 reach their respective power-ok (pok) thres hold values, device interrupts microcontroller. the circuit is designed such that the state machine initializes correctly even for v ery slow ramp rates on vsup of the order of 0.5v/min. power off normal receive only standby sleep host command (go to receiveonly) host command (go to normal) h o s t c o m m a n d ( g o t o s t a n d b y ) host command (go to receiveonly) h o s t c o m m a n d ( g o t o n o r m a l ) h o s t c o m m a n d ( g o t o s t a n d b y ) host command (go to sleep) temp< t jrecv and bus wake or local wake host command (go to sleep) h o s t c o m m a n d ( g o t o s l e e p ) temp > t jshut bus wake disabled temp>t jwarn bus transmitter disabled bus transmitter will be enabled on temp < t jrecv from any state power-up v s u p _ p o r _ r e s e t = = 0 v 3 p 3 _ r e s e t = = 1 & r e s e t t i m e o u t v 3 p 3 p o r t i m e o u t o r s t a r t u p w a t c h d o g t i m e o u t normal or receive_only or standby state v 3 p 3 _ r e s e t == 0 vsup_uv_flag = 1 or v5v_uv_flag =1 bus transceiver disabled vsup_uv_flag =1 or v5v_uv_flag= 1 bus transceiver disabled
www.austriamicrosystems.com/AS8650 revision 1.0 18 - 46 AS8650 datasheet - detailed description the power initialization sequence diagram is shown in figure 6 . after activating the powe r supply on vsup pin, the vsup_por _reset flag becomes inac tive (high) while th e voltage exceeds the vsup_por threshold. the dcdc output voltage v5v exceeds the v5v_ pokth thresholds after the dcdc settling time and the first voltage regulator (ldo1 ) will be activated with the v5v_pok set. if the voltage output at ldo1 (set to 2.5v on power-up) reaches the vldo1_pokth threshold, the porn_2_otp flag is set and otp register setting for the ldo1 is read. consequently the output voltage will be regulated to the actual otp settings. the initialization phase of the device is terminated after the preset output voltage level threshold is exceeded and the reset timeout is expired. after entering stand-by mode the host controller can switch the device in any operation mode through the i2c or spi interface. figure 6. initialization sequence vsup vsup_por_reset porn_2_otp load_otp_in_ prereg reset vldo1_pokth vsup_por tres = reset timeout 6 cycles of rc- oscillator v5v v5v_pok vldo1 vldo1_reset standby mode initialization device state normal mode startup watchdog vldo2 vldo3 intn v5v_pokth vldo2_pokth vldo3_pokth t ldo = ldo settling time t ldo = ldo settling time t dcdc = dcdc settling time vldo1_pokth
www.austriamicrosystems.com/AS8650 revision 1.0 19 - 46 AS8650 datasheet - detailed description 7.5 dcdc converter the high-efficiency, high-voltage, hysteretic step-down dcdc converter, operates in asynchronous mode and delivers 500ma of out put load to drive the three internal ldos and the can transceiver. the low- power architecture extends hold-up time in battery-backed and cr itical applications where maximum up-time over a wide input supply voltage range is needed, while still providing for high efficiencie s of up to 90% during peak current demands. 7.6 voltage regulator ldo1 the stability of the voltage output is below 2.5% over the full input range and temperature for load current up to 100 ma at 3 .3v. power input to this ldo is the v5v_ldo1 pin. this ldo is activated in normal, receive only or standby mode. it is switched off in sleep mode. 7.7 voltage regulator ldo2 the stability of the voltage output is below 2.5% over input range and temperature for load current up to 100 ma. the voltage regulator is programmable between 3.3v and 1.8v via i2c or spi interface. power in put to this ldo is the v5v_ldo2 pin. ldo2 is activated in normal and receive only mode. 7.8 voltage regulator ldo3 the stability of the voltage output is below 2.5% over input range and temperature for load current up to 100 ma. the voltage regulator is programmable between 3.3v and 1.8v via i2c or spi interface. power in put to this ldo is the v5v_ldo3 pin. ldo3 is activated in normal and receive only mode. 7.9 over-temperature monitor in normal mode, if the junction temperature reaches the over-temperature threshold t jwarn , a warning flag is set in the diagnostic register which can be accessed via the i2c and the spi interface and an interrupt is signalled on intn pin. the can transmitter is disabled an d the device remains in normal mode. if the junction temperature falls below t jrecv , the can transmitter is enabled. the warning flag is cleared in the diagnostic register and an interrupt is signalled at the intn pin. if the junction temperature exceeds the over-temperature thr eshold t jshut , the device enters sleep mode irrespective of the current mode and bus wake receiver (low power receiver) is disabled. as soon as th e temperature falls below t jrecv , the bus wake receiver (low power receiver) is switched on. 7.10 undervoltage reset undervoltage on vsup (brown out indication). if vsup voltage falls below vsup_uvth th reshold, the vsup_uv_flag is set and an interrupt at intn is generated. in this case the device enters into the stand-by mode. the ldo1 voltage regulator remains activ ated. two scenarios are possible at this stage: vsup is recovering: if vsup exceeds the vsup_ pokth threshold, the vsup_pok_flag is set and the device remains in stand-by mode. vsup is still falling: in this case the device continues to st ay in stand-by mode. if voltage falls below vsup_reset threshold, then the device enters power-off and the logic is reset. undervoltage on v5v. if the v5v falls below v5v_uvth thresh old, the v5v_uv_flag is set. once v5v returns to v5v_pokth threshold value, v5v_pok_flag is set. in case a flag is set, an interrupt is generated at the intn pin. if undervoltage on v5v occurs in normal or receive only modes then can transceiver is disabled and the device remains in its operation mode. undervoltage on ldo1. if the voltage level of ldo1 falls below the vldo1_uvth threshold value and device is not in sleep mode, the device enters into power-up state while reset signal is asse rted and the voltage regulator is still active. once the vldo1_pokt h threshold is reached, reset signal is de-asserted after reset timeout period and device enters into standby mode. undervoltage on ldo2. if the voltage level of the ldo2 falls below the vldo2_uvth threshold value a vldo2_uv_flag is set. an indication is given to microcontroller by setting a bit in interrupt register and giving interrupt on intn pin. once vldo2 retu rns to vldo2_pokth threshold value, vldo2_pok_flag is set. an indication is given to microcontroller by setting a bit in interrupt reg ister and giving interrupt on intn pin. undervoltage on ldo3. if the voltage level of the ldo3 falls below the vldo3_uvth threshold value a vldo3_uv_flag is set. an indication is given to microcontroller by setting a bit in interrupt register and giving interrupt on intn pin. once vldo3 retu rns to vldo3_pokth threshold value, vldo3_pok_flag is set. an indication is given to microcontroller by setting a bit in interrupt reg ister and giving interrupt on intn pin.
www.austriamicrosystems.com/AS8650 revision 1.0 20 - 46 AS8650 datasheet - detailed description figure 7. power-up and undervoltage sequence 7.11 reset block the reset block generates an exte rnal reset signal to re set the microcontroller and all other external circuits. the reset func tionality is explained in figure 8 . the reset block consists of a digita l buffer at the output. the reset signal is affected by vldo1_reset (during overload, reset on vldo1) and watch dog output. all conditions wh ich cause a drop of the vldo1 voltage will be detected from th e low voltage reset unit which in-turn generates a reset signal. figure 8. reset block functional waveform v5v_pokth v5v v5v_pok_flag v5v_uvth v5v_uv_flag dcdc supply vldo1_pokth vldo1 vldo1_reset vldo1_uvth ldo1 supply vsup_por vsup_reset vsup_uvth vsup_pokth vsup vsup_por_reset vsup_uv_flag vsup supply vsup still falling vsup_pok_flag vsup recovering vsup recovering vsup still falling vldo3_pokth vldo3 vldo3_pok_flag vldo3_uvth vldo3_uv_flag ldo3 supply vldo2_pokth vldo2 vldo2_pok_flag vldo2_uvth vldo2_uv_flag ldo2 supply vldo1 vsup vldo1_por t res t rr t>t jshut t www.austriamicrosystems.com/AS8650 revision 1.0 21 - 46 AS8650 datasheet - detailed description 7.12 can transceiver the AS8650 provides an advanced interface between the protocol controller and the physical bus in a controller area network (ca n) node. this is intended for automotive high-speed can application (up to 1 mbit/s), providing differential transmit capability to the bus a nd differential receive capability to the can controller. it is fully compatible to the iso 11898 standard and offers excellent electromagnetic compati bility (emc) performance. the can is a high speed, low complexity protocol with improved emi and emc performance. the can is a serial commun ication protocol efficiently supporting the control of mechatronic nodes in a distributive automotive application. the basic blocks of the can transceiver are described below: 7.12.1 bus driver this driver has the basic functionality of relaying the data from the microcontroller on to the can bus. the data on the can ne eds to have a controlled slew to reduced emi. a low side driver is used which has an inherent reverse polarity protection. it has a short-cir cuit current limitation. 7.12.2 normal receiver it relays the data from the can bus to the microcontroller in normal mode. 7.12.3 low power receiver it relays the data from the can bus to the microcontroller in low power mode state. 7.12.4 operating modes the can transceiver provides the following operating modes: normal: non low power mode receive only: non low power mode standby: low power mode sleep: low power mode normal mode. in this mode the transceiver is able to send and receive data signals on the bus. rxd reflects the bus data. receive only mode. in this mode the transceiver has the same behavior as in normal mode but the transmitter is disabled. standby mode or sleep mode. in this mode the transceiver is not able to send and receive data signals from the bus, but the wake up detector is active. the power consumption is significantly reduced res pect the non low power operation modes. the wake_remote r eflects the remote wake up detector output; wake_ local reflects the i nput signal on wake pin. 7.12.5 local wake-up event in all low power modes, if the voltage on the wake pin falls below v_lwuth for longer than t lw_filter , wake_local falls down. at the same time the biasing of the pin is switched to pull- down. if the voltage on the wake pin rises above v_lwuth for longer than t lw_filter , wake_local rises up. at the same time the biasing of the pin is switched to pull-up. in current application wake pin is initial ly pulled-down to ground using external resistor on power up. for valid wake-up, the wake pin needs a rising edge. table 14. operating modes state txd transmitter normal receiver low power receiver bust state normal l enabled enabled disabled dominant h enabled enabled disabled recessive rec only x disabled enabled disabled (canh, canl are not driven) standby x disabled disabled enabled (canh, canl are not driven) sleep x disabled disabled enabl ed (canh, canl are not driven)
www.austriamicrosystems.com/AS8650 revision 1.0 22 - 46 AS8650 datasheet - detailed description figure 9. wake input pin behavior 7.12.6 remote wake-up in all low power modes, if the differential voltage on the bus becomes recessive for longer than t_bus_wr, wake_remote rises up . if the differential volt age on the bus becomes do minant for longer than t_bus_wr, wake_remote fa lls down as shown in figure 10 . figure 10. remote wake-up event a remote wake request is detected after two dominant pulses with each pulse separated by a recessive pulse of at least t rec (wake) . the remote wake detection circuit is active in sleep and standby modes. the wake message pattern is shown in figure 11 . wake t l_wake pull up pull down t lw_filter pull up vsup local wake detected local wake detected t l_wake t lw_filter wake_local v_lwuth v_rxd_h v_rxd_l vin_diff wake_remote vio t_bus_wr t_bus_wr
www.austriamicrosystems.com/AS8650 revision 1.0 23 - 46 AS8650 datasheet - detailed description figure 11. wake message pattern 7.13 internal flags the AS8650 supports internal flags to indicate the failures in the system. if any of these flag is set an interrupt is generate d on intn pin. 7.13.1 vsup_uv_flag this is a vsup undervoltage flag. this flag is set when vsup falls below the vsup_uvth threshold. when this flag is set the dev ice enters into standby mode and bus transceiver is switched off to save power. when vsup recovers and raises above vsup_pokth threshold the vsup_uv_flag is reset. 7.13.2 vsup_pok_flag this is a vsup power ok flag. this indicates the vsup recovery from undervoltage condition. when the vsup rises above vsup_pokt h threshold, this flag is set. this indicates the microcontroller that undervoltage condition on battery is cleared. 7.13.3 v5v_uv_flag this is a v5v undervoltage flag. this flag is set when v5v falls below the v5v_uvth threshold. when this flag is set the device enters into standby mode and bus transceiver is switched off to save power. when v5v recovers and raises above v5v_pokth threshold the v5v_uv_flag is reset. 7.13.4 v5v_pok_flag this is a v5v power ok flag. this indicates the v5v recovery from undervoltage condition. when the v5v rises above v5v_pokth th reshold, this flag is set. this indicates the microcontroller that undervoltage condition on dcdc converter is cleared. 7.13.5 vldo2_uv_flag this is a vldo2 undervoltage flag. this flag is set when vldo2 fa lls below the vldo2_uvth threshold. when vldo2 recovers and ra ises above vldo2_pokth threshold the vldo2_uv_flag is reset. 7.13.6 vldo2_pok_flag this is a vldo2 power ok flag. this indicates the vldo2 recovery from undervoltage condition. when the vldo2 rises above vldo2_ pokth threshold this flag is set. this indicates the microcontroller that undervoltage condition on ldo2 is cleared. 7.13.7 vldo3_uv_flag this is a vldo3 undervoltage flag. this flag is set when vldo3 fa lls below the vldo3_uvth threshold. when vldo3 recovers and ra ises above vldo3_pokth threshold the vldo3_uv_flag is reset. 7.13.8 vldo3_pok_flag this is a vldo3 power ok flag. this indicates the vldo3 recovery from undervoltage condition. when the vldo3 rises above vldo3_ pokth threshold this flag is set. this indicates the microcontroller that undervoltage condition on ldo3 is cleared. 7.13.9 bus wake_up flag the bus wake_up flag is set when the device detects a remote wake-up (bus message) request. the remote wake-up request is detec ted when pattern shown in figure 11 is found on wake_remote port of low power receiver. this indicates the microcontroller about the bus wake event. wake_remote canh canl wake_remote_flag remote wake detected >t dom(wake) >t rec(wake) >t dom(wake) >t rec(wake) dominant reccessive dominant reccessive
www.austriamicrosystems.com/AS8650 revision 1.0 24 - 46 AS8650 datasheet - detailed description 7.13.10 local wake_up flag the local wake_up flag is set when the device detects a local wake-up request on wake pin. a local wake-up request is detected when a logic state change on pin wake as shown in figure 9 . this indicates the microcontroller about the local wake event. 7.13.11 ovt_warning flag the ovt_warning flag is set when temperature exceeds t jwarn . this indicates the microcontroller about temperature exceeding warning levels. 7.13.12 ovt_recover flag the ovt_recover flag is set when temperature falls back below t jrecv . this indicates the microcontroller about temperature falling back below recovery levels. 7.13.13 bus failure flags the bus failure flag is set if the can transceiver detects a bus line short-circuit condition to vsup, v5v_ldo1 or gnd. such po ssible conditions are indicated to microcontroller through these flags. all these flags are cleared on microcontroller read. if the fault conditi on still exist after microcontroller read, the particular flag is set again. the device still be working in the current state. the microcontroller t akes appropriate action on reading of these flags. canh_short_gnd. this flag indicates over current condition on pin canh. for example short to ground on pin canh. when the output current on pin canh exceeds the threshold oc_canh_th then the ou tput oc_canh switches on high leve l after a filter time t_oc_ca nh. canh_short_vsup. this flag indicates low current on pin canh. for example open load or short to vsup on pin canh. when the output current on pin canh falls below the threshold lc_canh_th then the output lc_canh switches on high level after a filter time t_l c_canh. canl_short_vsup. this flag indicates over current on pin canl. for example short to vsup on pin canl. when the output current on pin canl exceeds the threshold oc_canl_th, then the output oc_c anl switches on high level after a filter time t_oc_canl. canl_short_gnd. this flag indicates low current on pin canl. for example open load or short to ground on pin canl. when the output current on pin canl falls the threshold lc_canl_th then the output lc_canl switches on high level after a filter time t_lc_canl . 7.13.14 local failure flags the AS8650 prevents the system from four kinds of local failure s without disturbing the bus network. the four failures are txd dominant clamping, rxd recessive clamping, txd & rxd short, and bus dominant clamping. all these failures are indicated to microcontroll er through flags. txd_dom_clamp flag. a permanent low-level on pin txd (due to a hardware or software application failure) would drive the bus into a permanent dominant state, blocking bus network communication. if pin txd remains at a low level for longer than the txd dominan t time-out period t txdc(dom) , the device disables the transmitter of bus transceiver and txd_dom_clamp flag is set. the device prevents such bus network lock-up by disabling the transmitter of the transceiver. the device will not change the functional state. the transmitt er remains disabled until the local failure flag is cleared by host command. the flag is cleared on microcontroller read. rxd_rec_clamp flag. if pin rxd is shorted to vldo1, the rxd pin is permanently clamped to recessive state. the bus controller can not see the bus dominant state and start sending message thinking bus is idle. this disturbs the bus. this rxd recessive clamping i s detected by the device when bus is at dominant state. on detection of this a failure rxd_rec_clamp flag is set and the transmitter is disab led. the flag is cleared on microcontroller read. the transmitter is enabled by host command. txd_rxd_short flag. the txd_rxd short circuit would result in a dead-lock situation clamping the bus dominant. for example the transceiver receives a dominant signal, rxd outputs a dominant level. because of the short circuit, txd reflects a dominant sig nal, retaining the dominant bus state. as a result txd and the bus are clamped continuously dominant. the resulting effect is the same as for the continuously clamped dominant txd signal. the txd dominant timeout interrupts the deadlock situation by disabling the transmitter and the tx d_rxd short condition is differentiated. the bus becomes recessive again and txd will be recessive if it is not driven by microcontroller. however, the failure scenario may still exist and with the next dominant signal on the bus the described procedure will start again. the device keeps the transmitter off after detection of txd_rxd short fault and keeps updating this flag status. the microcontr oller has to send 2 consecutive low pulses of duration 500ns with high period of 500ns in-between, in regular intervals to check short circuit re covery. this way a local txd/rxd short circuit will not disturb the communication of the remaining bus system. bus_dom_clamp flag. in the case of a short circuit from bus to gnd, the circuit for the bus receiver senses dominant signal continuously even if there is no dominant transmitting node. the result may be a permanently dominant clamped bus. the device detects and re ports a bus dominant clamping situation to microcontroller through bus_dom_clamp flag. if the receiver detects a bus dominant phase of long er than the bus dominant time out t busc(dom) bus_dom_clamp flag is set. the flag is cleared on microcontroller read.
www.austriamicrosystems.com/AS8650 revision 1.0 25 - 46 AS8650 datasheet - detailed description 7.14 watchdog (wd) the wd has the following three monitory timing functions: start-up watchdog: gives opportunity to microcontroller to initialize the system. window watchdog: detects too early or too late microcontroller software response (loops and hangs). time-out watchdog: detects too very long response from microcontroller. 7.14.1 start-up wa tchdog behavior following any reset event the watchdog is used to monitor the ecu start-up procedure. once the reset is released the watchdog c ounter will start. in case the watchdog is not properly served (a trigger from microcontroller) within twd(init), another reset is forced o n reset pin and the monitoring procedure is restarted. the watchdog will give three opportunities to microcontroller to initialize the system. in c ase the watchdog is not properly served for three times, then the system enters into sleep mode. 7.14.2 window watchdog behavior whenever the device enters normal mode, the window mode of the watchdog is activated. this ensures that the microcontroller ope rates within the required speed; a too fast as well as a too slow operatio n will be detected. watchdog triggering using the window watchdog is illustrated in figure 12 . figure 12. window watchdog triggering the AS8650 provides 8 different period timings. this timing can be changed through digital interface when desired. the period c an be changed within any valid trigger window. whenever the watchdog is triggered within the window time t wd_trig , the timer will be reset to start a new period. the watchdog window is defined to be between 50% and 100% of the nominal programmed watchdog period. any too early (trigger in non- trigger window) or too late wa tchdog trigger will result an immediate system reset on reset pin and watchdog en tering start-up watchdog mode. during undervoltage condition on vldo1 the watchdog timer is disabled. trigger window non-trigger window t wd_no_trig t wd_trig t wwd_period trigger restarts period 50% 100% last trigger point earliest trigger point latest trigger point trigger window non-trigger window 50% 100% earliest trigger point latest trigger point trigger restarts period ( with new period if desired) new period spi trigger spi trigger unwanted trigger (reset generated, watchdog enter start-up mode)
www.austriamicrosystems.com/AS8650 revision 1.0 26 - 46 AS8650 datasheet - detailed description 7.14.3 time-out watchdog behavior whenever the AS8650 operates in standby mode, active watchdog operates in time-out watchdog mode. the watchdog has to be trigge red within the actual programmed period time t wd_tout_period . the device provides 8 different possible periods for programming through digital interface. if the microcontroller fails to trigger the watchdog within trigger range then the system reset is generated on rese t pin and watchdog enters into start-up watchdog mode. the time-out watchdog function is illustrated in figure 13 . figure 13. time-out watchdog triggering 7.15 interrupt generation the pin intn is an interrupt output. the intn is forced low if one bit in the interrupt register is set. the interrupt register bits are cleared when the microcontroller clears the corresponding interrupt source register. the interrupt register will also be cleared during a sy stem reset (reset low). as there are microcontrollers with level sensitive or edge sensitive interrupt port, pin intn will be high for at least t intn after any of the interrupt source register is cleared. the interrupt source regist er is cleared through write operation by overwriting 1 in to r espective set bits position. without further interrupts within tintn pin intn stays high, otherwise it will revert to low again. the interrupt register indicates the cause of an interrupt event. there are two levels of interrupt registers. first level regi ster indicates the source region of interrupt and the second level register indicates the exact source of interrupt. with this structured interrupt, the microcontroller can trace source of interrupt by two read operations instead of polling for source of interrupt and also interrupts can be prioritized by microcontroller. the interrupt register structure is given in figure 14 . the register is cleared through digital interface write operation and upon any reset event. the hardware ensures no interrupt event is lost in case there is a new interrupt forced while reading the register. trigger window non-trigger window t wd_no_trig t wd_trig t wwd_period trigger restarts period 50% 100% last trigger point earliest trigger point latest trigger point trigger window non-trigger window 50% 100% earliest trigger point latest trigger point trigger restarts period ( with new period if desired) new period spi trigger spi trigger unwanted trigger (reset generated, watchdog enter start-up mode)
www.austriamicrosystems.com/AS8650 revision 1.0 27 - 46 AS8650 datasheet - detailed description figure 14. interrupt register structure 7.16 status registers the AS8650 has three flag status registers and one reset reason r egister. the flag status registers indicate the current status of flags which are related to respective interrupt source registers. the flag status registers are bus status register, temperature status reg ister and supply status register. the microprocessor can read these registers any time to check the status of device. the function of each flag is listed in register space description in subsequent sections. a reset reason register indicates the reasons for reset generation. once the reset pin goes low, the reason of this reset event is stored in reset reason register. when reset is released microprocessor can read this register to know the cause for last reset signal. th e reset reason register is cleared once microprocessor reads this register through read operation. the bits functionality of this regis ter is explained in register space description table. supply related interrupt bus and local failure interrupt wake-up, temperature and ldo timeout interrupt i1 i2 i3 r r r r r interrupt register vsup_uv_flag vsup_pok_flag d1 d7 d6 d2 d3 d4 d5 d0 v5v_uv_flag v5v_pok_flag v2p8_uv_flag v2p8_pok_flag v1p8_uv_flag v1p8_pok_flag interrupt source registers canh_short_gnd canh_short_vcc canl_short_vcc canl_short_gnd rxd_rec_clamp txd_dom_clamp d1 d7 d6 d2 d3 d4 d5 d0 txd_rxd_short bus_dom_clamp wake_up local wake_up ovt_warning d1 r rd2 d0 rr d3 ovt_recovery reserved reserved reserved reserved
www.austriamicrosystems.com/AS8650 revision 1.0 28 - 46 AS8650 datasheet - application information 8 application information device interfaces. there are two ways to communicate with AS8650, one is 4 wires spi and other is i2c. the selection between these two interfaces is through i2c_en pin, as shown in table 15 . the pins cs, sclk, sdi, and sdo are used for spi interface. for i2c interface, sclk is used as i2c clock and sda is used as i2c data line. pins sclk i2c / sclk spi and sda i2c / sdi spi are multiplexed for both spi and i2c interface. since i2c_en is a digital input pin, it has to be connected either to vldo1 or gnd. note: i2c_en should not be changed during a i2c/spi read/write operation. maximum switching delay between i2c and spi is 8s. 8.1 serial peripheral interface the serial peripheral interface (spi) provides the communication link with the microcontroller. the spi is configured for half- duplex data transfer. the spi provides access to configuration registers, control regi sters, and diagnostic registers. the modes of the AS8650 are ch anged by writing required code in to mode control register through spi. the spi is also used to enter into test and otp modes. this interface is only slave interface and only master can initiate spi operation. the spi can work on both the clock polarities. the polarity of the clock depends on the value of sclk at the falling edge of cs . at the falling edge of cs if sclk is ?1? then the spi is positive edge triggered and if the sclk is ?0? then spi is negative edge triggered lo gic (see table 16) . the spi protocol frame is divided in to two fields, the header field and the data field. the header field is 1 byte long contai ning a read/write command bit, 5 address bits and 2 reserved bits. the data field is of one data byte. the spi frame format is shown in figure 15 . in the data phase msb is sent first and lsb is sent last. figure 15. spi frame format table 15. device interface selection i2c_en description low interface is 4-wire spi high interface is i2c table 16. spi clock polarity cs sclk description low high serial data is transferred at falling edge and sampled at rising edge of sclk low low serial data is transferred at rising edge and sampled at falling edge of sclk r/w a0 a1 a2 a3 a4 header field data field 1 byte reserved bits 5 bits address 0 ? write 1 ? read 0 0 d7 d6 d5 d4 d3 d2 d1 d0
www.austriamicrosystems.com/AS8650 revision 1.0 29 - 46 AS8650 datasheet - application information 8.1.1 spi write operation the spi write operation begins with clock polarity selection at negative edge of cs, given in table 16 . once the clock polarity is selected the spi write command is given by providing ?0? in r/w bit of the header field in first sampling edge at sdi pin. the 5 bits address of register to be written is provided at sdi pin in next five consecutive sampling edges of sclk. the first 2 bits in header fields are reserved and set to 0. the data to be written is followed by last bit of header field. with each sampling edge a bit is sampled starting from msb to lsb. during comp lete spi write operation the cs has to be low. the spi write operation ends with positive edge of cs. the wave form for spi write operation wi th single data byte is shown in figure 16 and figure 17 . figure 16. spi write operation with negative clock polarity and 1 byte of data field figure 17. spi write operation with positive clock polarity and 1 byte of data field r1 r0 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 sclk sdi sdo cs sampling edge high impedance sate sclk sdi sdo cs r1 r0 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 sampling edge high impedance sate
www.austriamicrosystems.com/AS8650 revision 1.0 30 - 46 AS8650 datasheet - application information 8.1.2 spi read operation the spi read operation also begins with clock polarity selection at negative edge of cs, given in table 16 . once the clock polarity is selected the spi read command is given by providing ?1? in r/w bit of the header field in first sampling edge at sdi pin. the 5 bits address of register to be read is provided at sdi pin in next five consecutive sampling edges of sclk. the first 2 bits in header fields are reserved and set to 0. the read data is followed by last bit of header field on sdo pin. with each sampling edge a bit can be read on sdo pin starting from msb to lsb. during complete spi read operation the cs has to be low. the spi read operation ends with positive edge of cs. the wave form for spi r ead operation with single data byte is shown in figure 18 and figure 19 . figure 18. spi read operation with negative clock polarity and 1 byte of data field figure 19. spi read operation with positive clock polarity and 1 byte of data field d7 d6 d5 d4 d3 d2 d1 d0 r1 r0 a4 a3 a2 a1 a0 sclk sdi cs sdo sampling edge high impedance sate sclk sdi cs sdo r1 r0 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 sampling edge high impedance sate
www.austriamicrosystems.com/AS8650 revision 1.0 31 - 46 AS8650 datasheet - application information 8.1.3 spi timing diagram figure 20. timing diagram for spi write operation figure 21. timing diagram for spi read operation cs sdi sdo sclk ... ... ... clk polarity datai datai datai ... t sclkl t sclkh t cphd t cps t dis t dih t csh cs sclk sdi sdo datai datai datao (d7 n )datao (d0 0 ) t sclkl t sclkh t dod t dohz
www.austriamicrosystems.com/AS8650 revision 1.0 32 - 46 AS8650 datasheet - application information 8.2 inter-integrated circuit (i2c) interface i2c is a bidirectional 2 line bus interface with a serial data line (sda) and a serial clock line (sclk) for inter ic control. this interface is only slave interface and only microcontroller can start and stop the i2c operation. the overview of i2c protocol is shown in figure 22 . a high to low transition on sda line while sclk is high is the start (s) conditi on and a low to high transition on sda line while sclk is hig h is the stop (p) condition, as shown in figure 22 . the start and stop conditions should always be generated by the microcontroller. after the start condition, microcontroller has to make sure that data on sda line must be stable during the high period of sclk. the data should only change when sclk line is low. the bus is busy after the start condition and it is free after the stop condition. any number of data bytes can be transmitted between start and stop. each byte is followed by an acknowledgement (which is the ninth bit). the data trans mitter always receives an acknowledgement from the data receiver at end of each byte. the data transmitter releases the sda bus at sta rt of low period of 8th clock pulse and data receiver acknowledges by pulling the sda to low during the low period of the sclk. the data receiver releases the bus at start of low period of 9th clock pulse of the sclk and data transmitter gets the data bus.the AS8650 does n ot support general call address, start byte and high-speed mode. figure 22. i2c bus protocol 8.2.1 i2c write operation after the start condition, microcontroller has to send, in the first byte, the 7-bit slave address and 0 into the r/w bit as sh own in figure 23 . the microcontroller has to send the address of the register to be written in the second byte. the first 3 msb bits are reserved and remaining 5 bits are used as address bits. the data is sent starting from msb to lsb. the AS8650 sends acknowledgement on 9th clock pulse. in the ne xt byte (3rd byte) microcontroller has to send the data to be written into addressed register. if it is a single write operation, after rece iving the acknowledgment from AS8650, microcontroller has to send start or stop condition, as shown in figure 23 . in case of auto increment write operation, microcontroller should not generate start or stop condition after the third byte. if microcontroller continuously wr ites then address pointer rolls back to the starting register address after reaching the last register address. data bytes coming from the microc ontroller are written at the consecutive address locations, starting from the address sent in first data byte. after each data byte, direction of the bus line changes and AS8650 acknowledges by pulling the sda line low. to terminate the write operation microcontroller has to generate stop or repea ted start condition. for details, see figure 24 . figure 23. i2c write operation sda s 12 8 9 sclk msb ack 34 56 7 12 8 9 34 56 7 r/w 7 bit slave address lsb 8 bit data 12 8 9 34 56 7 s or p 8 bit data ack ack 12 8 9 sclk msb sda 34 56 7 12 8 9 34 56 7 lsb 12 8 9 34 56 7 a aa acknowledge from slave acknowledge from slave acknowledge from slave register address data to register s or p r/w slave address s a0 a1 a2 a3 a4
www.austriamicrosystems.com/AS8650 revision 1.0 33 - 46 AS8650 datasheet - application information figure 24. i2c auto-increment write operation 8.2.2 i2c read operation after the start condition, microcontroller has to send, in the first byte, the 7-bit slave address and 0 into the r/w bit as sh own in figure 25 . the microcontroller has to send the address of the register to be written in the second byte. the first 3 msb bits are reserved and remaining 5 bits are used as address bits. the data is sent starting from msb to lsb. after receiving the acknowledgement on the 9th clock pulse, mi crocontroller has to send on the sda line repeated start or stop, as shown in figure 25 . if microcontroller sends stop then microcontroller has to send start again. if microcontroller sends repeated start then there is no need to generate start again. the microcontroller again h as to send the 7-bit slave address and writes 1 into the r/w bit (8th bit). now AS8650 sends data of the corresponding addressed register in the next eight clock cycles. in case of single read, microcontroller does not acknowledge on the 9th clock pulse and generates start or stop c ondition after the ninth clock pulse. if it is an auto increment read operation, microcontroller acknowledges on the 9th clock pulse and as865 0 sends data from the consecutive address locations, see figure 25 . if microcontroller continuously reads then address pointer rolls back to the starting register address after reaching the last register address. in the data phase msb is sent first and lsb is sent last. after each data byt e, microcontroller has to send the acknowledgement. the microcontroller can terminate the auto read operation by not generating acknowledgement fo r the last byte that was sent by the AS8650 and generates stop or repeated start condition after the 9th clock pulse. figure 25. i2c read operation 12 8 9 sclk msb sda master transmitter 34 56 7 12 8 9 34 56 7 lsb 12 8 9 34 56 7 a aa acknowledge from slave acknowledge from slave acknowledge from slave data to register s or p data to register + n r/w slave address s register address a0 a1 a2 a3 a4 12 8 9 sclk msb sda 34 56 7 12 8 9 34 56 7 lsb a a acknowledge from slave acknowledge from slave register address s or p w slave address 12 8 9 sclk msb sda 34 56 7 12 8 9 34 56 7 lsb a a acknowledge from slave acknowledge from master data byte r slave address 0 1 s s s or p a0 a1 a2 a3 a4
www.austriamicrosystems.com/AS8650 revision 1.0 34 - 46 AS8650 datasheet - application information figure 26. i2c auto-increment read operation 8.3 digital timing specification spi protocol. table 17. spi timing parameters symbol parameter conditions min typ max units general br spi bit rate 1 mbps t sclkh clock high time 500 ns t sclkl clock low time 500 ns write operation parameters t dis data in setup time 20 ns t dih data in hold time 10 ns t csh cs hold time 40 ns read operation parameters t dod data out delay 80 ns t dohz data out to high impedance delay time for the spi to release the sdo bus 80 ns timing parameters for sclk polarity identification t cps clock setup time (clk polarity) setup time of sclk with respect to cs falling edge 20 ns t cphd clock hold time (clk polarity) hold time of sclk with respect to cs falling edge 20 ns 12 8 9 sclk msb sda 34 56 7 12 8 9 34 56 7 lsb a a acknowledge from slave acknowledge from master data byte 1 r slave address 12 8 9 34 56 7 a no acknowledge from master last data byte data byte n 12 8 9 sclk msb sda 34 56 7 12 8 9 34 56 7 lsb a a acknowledge from slave acknowledge from slave register address w slave address 0 1 s or p s s s or p a 0 a 1 a 2 a 3 a 4
www.austriamicrosystems.com/AS8650 revision 1.0 35 - 46 AS8650 datasheet - application information i2c protocol. electrical characteristics of sda & sclk bus lines for f/s mode 1. cb = capacitance of one bus line in pf. 2. the maximum t f for the sda and sclk bus lines quoted in table 19 (300ns) is longer than the specified maximum t of for the output stages (250ns). this allows for any series protection resistors to be connected between the sda/sclk pins and the sda/sclk bus lines without exceeding the maximum specified t f . 3. i/o pins of fast-mode devices must not obstruct the sda and sclk lines if vldo1 is switched off. characteristics of the sda and sclk bus lines for f/s mode i2c bus. table 18. i2c electrical parameters symbol parameter standard fast units min max min max v il low level input voltage: vldo1related input levels 0.3v*ldo1 0.3v*ldo1 v v ih high level input voltage: vldo1-related input levels 0.7v*ldo1 0.7v*ldo1 v v hys hysteresis of schmitt trigger input n/a n/a 0.05v*ldo1 v v ol1 low level output voltage (open drain or open collector) at 3ma sink current 0.4 0.4 v t of output fall time from v ihmin to v ilmax with a bus capacitance from 10pf to 400pf 250 (see footnote 2) 20 + 0.1c b (see footnote 1) 250 (see footnote 2) ns (lab tested only) t sp pulse width of spikes which must be suppressed by the input filter n/a n/a 50 ns i i input current of each i/o pin with an input voltage between 0.1vldo1 and 0.9vldo1 maximum -10 10 -10 (see footnote 3) 10 (see footnote 3) a c i capacitance for each i/o pin 10 10 pf (guaranteed by design) table 19. i2c timing parameters symbol parameter standard fast units min max min max (see footnote 1) f sclk sclk clock frequency 0 100 0 400 khz t hd_sta hold time (repeated) start condition. after this period, the first clock pulse is generated 4-0.6- s t low low period of the sclk clock 4.7 - 1.3 - s t high high period of the sclk clock 4.0 - 0.6 - s t su_sta set-up time for a repeated start condition 4.7 - 0.6 - s t su_dat data set-up time 250 - 100 (see footnote 2) -ns t hd_dat data hold-time 0 (see footnote 5) 3450 (see footnote 3) 0 (see footnote 5) 900 (see footnote 3) ns t r rise time of sda and sclk signals - 1000 20+ 0.1c b (see footnote 4) 300 ns
www.austriamicrosystems.com/AS8650 revision 1.0 36 - 46 AS8650 datasheet - application information 1. all values referred to v ihmin and v ilmax levels (see table 18) . 2. a fast mode i2c bus device can be used in standard mode i2c bus system, but the requirement t su_dat 250ns must then be met. this will automatically be the case if the device do not stretch the low period of the sclk signal. if such a device does stret ch the low period of the sclk signal, it must output the next data bit to the sda line t rmax . t su_dat = 1000 + 250 = 1250ns (according to standard mode i2c bus specification) before the sclk line released. 3. the maximum t hd;dat has only to be met if the device does not stretch the low period (t low ) of the sclk signal. 4. c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times according to table 18 allowed. 5. this device internally provides a hold time of at least 300ns for the sda signal to bridge the undefined region of the fall ing edge of the sclk. figure 27. definition of i2c timing parameters t f fall time of sda and sclk signals - 300 20+ 0.1c b (see footnote 4) 300 ns t su_sto set-up time for stop condition 4.0 - 0.6 - s t buf bus free time between a stop and start condition 4.7 - 1.3 - s c b capacitive load for each bus line - 400 - 400 pf v nl noise margin at the low level for each connected device (including hysteresis) 0.1v*ldo1 - 0.1v*ldo1 - v nh noise margin at the high level for each connected device (including hysteresis) 0.2v*ldo1 - 0.2v*ldo1 - table 19. i2c timing parameters symbol parameter standard fast units min max min max (see footnote 1) t low sclk sda t f t r t f t high t su_dat s t hd_sta t su_sta t hd_dat t buf t r t su_sto sr ps t sp
www.austriamicrosystems.com/AS8650 revision 1.0 37 - 46 AS8650 datasheet - application information 8.3.1 system specification and timings table 20. system timing parameters symbol parameter conditions min typ max units wake-up timing tdom(wake) minimum dominant pulse for can wake-up detection (remote wake) 5s trec(wake) minimum recessive pulse for can wake-up detection (remote wake) 5s tl_wake time between edge on wake pin to local wake detection 32 s tlw_filter time between edge on wake pin to wake_local signal (filter on wake pin) 0.75 5 s tr_wake remote wake detection time from the valid pattern detection 24 s tintn intn pin high time 7s v_lwuth local wake threshold input 24v local failure related timing ttxdc(dom) txd dominant time-out period 600 1000 1400 s tbusc(dom) bus dominant clamping time-out period 600 1000 1400 s watchdog timing & timeouts twd(init) start-up watchdog time-out (initialization time) 300 ms twd_trig window watchdog trigger window twwd_period is defined in wwd register 0.375 0.5 0.625 twwd_period
www.austriamicrosystems.com/AS8650 revision 1.0 38 - 46 AS8650 datasheet - application information 8.4 register space the AS8650 register space consists of configuration registers, control registers and diagnostic registers. all of these registe rs are accessible through spi or i2c commands. table 21. configuration registers addr register name por value bit type description 0x00 reserved reserved 0x01 reserved reserved 0x02 wd access control register 0000_0000 por_vldo1 d[7:0] r/w 0101_10 10 wd configuration register access enabled else wd configuration register access disabled 0x03 wd configuration register 0000_1001 por_vsup d[7:6] r/w 01 wd disabled else wd enabled d[5:3] time-out watchdog mode window period twd_tout_period . (accuracy of the timings is 25%) 000 80 ms 001 160 ms 010 320 ms 011 480 ms 100 800 ms 101 1000 ms 110 2000 ms 111 4000 ms d[2:0] window watchdog mode window period twwd_period (50% of above value is trigger window) 000 10 ms 001 40 ms 010 80 ms 011 120 ms 100 160 ms 101 240 ms 110 320 ms 111 400 ms 0x04 wd trigger register 0000_0000 por_vldo1 d[7:1] w reserved d[0] watchdog trigger bit. the microcont roller set this bit within the required window of watchdog timer. after this internal counter is reset and this bit is cleared internally.
www.austriamicrosystems.com/AS8650 revision 1.0 39 - 46 AS8650 datasheet - application information 0x05 device configuration register 0110_1101 por_vsup d[7] r/w 0 ldo3 disable in standby mode 1 ldo3 enable in standby mode d[6] 0 ldo3 disable in receive only mode 1 ldo3 enable in receive only mode d[5] 0 ldo3 disable in normal mode 1 ldo3 enable in normal mode d[4] 0 ldo2 disable in standby mode 1 ldo2 enable in standby mode d[3] 0 ldo2 disable in receive only mode 1 ldo2 enable in receive only mode d[2] 0 ldo2 disable in normal mode 1 ldo2 enable in normal mode d[1] 0 dcdc disable in sleep mode 1 dcdc enable in sleep mode d[0] 0 bus with low slew rate 1 bus with high slew rate 0x06 mode control register 0000_0000 por_vsup d[7:6] r/w reserved d[5:4] device state (read-only values) 0 device in stand by mode 1 device in normal mode 10 device in receive only mode d[3:2] reserved d[1:0] 00 stand by mode 01 normal mode 10 receive only mode 11 sleep mode 0x07 interrupt register 0000_0000 por_vsup d[7:3] r reserved d[2] 0 no interrupt 1 supply related interrupt. the source of interrupt is known by reading interrupt source register 3 d[1] 0 no interrupt 1 wake-up & temperature related interrupt. the source of interrupt is known by reading interrupt source register 2 d[0] 0 no interrupt 1 bus & local failure related interrupt. the source of interrupt is known by reading interrupt source register 1 table 21. configuration registers addr register name por value bit type description
www.austriamicrosystems.com/AS8650 revision 1.0 40 - 46 AS8650 datasheet - application information 0x08 interrupt source register 1 0000_0000 por_vsup d[7] r/w 0 no interrupt 1 interrupt due to bus clamped to dominant d[6] 0 no interrupt 1 interrupt due to short txd & rxd pins d[5] 0 no interrupt 1 interrupt due to rxd pin clamped to recessive d[4] 0 no interrupt 1 interrupt due to txd pin clamped to dominant d[3] 0 no interrupt 1 interrupt due to canl pin shorted to vcc d[2] 0 no interrupt 1 interrupt due to canl pin shorted to gnd d[1] 0 no interrupt 1 interrupt due to canh pin shorted to gnd d[0] 0 no interrupt 1 interrupt due to canh pin shorted to vcc 0x09 interrupt source register 2 0000_0000 por_vsup d[7:4] reserved d[3] 0 no interrupt 1 interrupt due to junction temperature falling back below t jrecv d[2] 0 no interrupt 1 interrupt due to junction temperature exceeding t jwarn d[1] 0 no interrupt 1 interrupt due to local wa ke up event on wake pin d[0] 0 no interrupt 1 interrupt due to wake up by bus message (remote wake) table 21. configuration registers addr register name por value bit type description
www.austriamicrosystems.com/AS8650 revision 1.0 41 - 46 AS8650 datasheet - application information 0x0a interrupt source register 3 0000_0000 por_vsup d[7] r/w 0 no interrupt 1 interrupt due to vldo3_pok_flag set d[6] 0 no interrupt 1 interrupt due to vldo3_uv_flag set d[5] 0 no interrupt 1 interrupt due to vldo2_pok_flag set d[4] 0 no interrupt 1 interrupt due to vldo2_uv_flag set d[3] 0 no interrupt 1 interrupt due to v5v_pok_flag set d[2] 0 no interrupt 1 interrupt due to v5v_uv_flag set d[1] 0 no interrupt 1 interrupt due to vsup_pok_flag set d[0] 0 no interrupt 1 interrupt due to vsup_uv_flag set 0x0b reserved 0000_0000 por_vsup d[7:0] reserved 0x0c bus status register 0000_0000 por_vsup d[7] r bus clamped to dominant d[6] txd & rxd pins short d[5] rxd pin clamped to recessive d[4] txd pin clamped to dominant d[3] canl pin shorted to vcc d[2] canl pin shorted to gnd d[1] canh pin shorted to gnd d[0] canh pin shorted to vcc 0x0d temperature status register 0000_0000 por_vsup d[7:2] r reserved d[1] otm 140 recovery flag d[0] otm 160 warning flag 0x0e supply status register 1010_1010 por_vsup d[7] r vldo3_pok_flag d[6] vldo3_uv_flag d[5] vldo2_pok_flag d[4] vldo2_uv_flag d[3] v5v_pok_flag d[2] v5v_uv_flag d[1] vsup_pok_flag d[0] vsup_uv_flag table 21. configuration registers addr register name por value bit type description
www.austriamicrosystems.com/AS8650 revision 1.0 42 - 46 AS8650 datasheet - application information 0x0f reset reason register 0000_0000 por_vsup r these bits are cleared on microcontroller read d[7] reserved d[6] sleep mode exit by local wake up on wake pin d[5] sleep mode exit by remote wake d[4] window watchdog failure d[3] timeout watchdog failure d[2] start-up watchdog failure d[1] undervoltage on vldo1 d[0] otm shutdown flag 0x10 backup register 0000_0000 por_vsup d[7:0] r/w otp_bits[32:25] / mcu backup data 0x11 d[7:0] otp_bits[40:33] / mcu backup data 0x12 d[7:0] otp_bits[48:41] / mcu backup data 0x13 d[7:0] otp_bits[56:49] / mcu backup data 0x14 d[7:0] {1?b0,otp_bits[63:57]} / mcu backup data 0x15 d[7:0] {2'd0, slave address[6:1]}/mcu backup data 0x16 d[7:0] 10bit_slave_address[3:0]/mcu backup data 0x17 d[7:0] mcu backup data table 21. configuration registers addr register name por value bit type description
www.austriamicrosystems.com/AS8650 revision 1.0 43 - 46 AS8650 datasheet - package drawings and markings 9 package drawings and markings the device is available in a 36-pin qfn (6x6x0.9) package. figure 28. drawings and dimensions marking: yywwixx. yy ww i xx last two digits of the current year manufacturing week assembly plant identifier assembly traceability code symbol min nom max a 0.80 0.90 1.00 a1 0 0.02 0.05 a3 - 0.20 ref - l 0.35 0.40 0.45 l1 0 - 0.15 b 0.18 0.25 0.30 d 6.00 bsc e 6.00 bsc e 0.50 bsc d2 4.60 4.70 4.80 e2 4.60 4.70 4.80 aaa - 0.15 - bbb - 0.10 - ccc - 0.10 - ddd - 0.05 - eee - 0.08 - fff - 0.10 - n36 notes: 1. dimensions and tolerancing conform to asme y14.5m-1994 . 2. all dimensions are in millimeters, angle is in degrees. 3. dimension b applies to metallized terminal and is measured between 0.25 and 0.30mm from terminal tip. dimension l1 represents terminal full back from package edge up to 0.15mm is acceptable. 4. coplanarity applies to the exposed heat slug as well as the terminal. 5. radius on terminal is optional. 6. n is the total number of terminals. AS8650 yywwixx
www.austriamicrosystems.com/AS8650 revision 1.0 44 - 46 AS8650 datasheet - revision history revision history note: typos may not be explicitly mentioned under revision history. revision date owner description 1.0 29 nov, 2010 hgl initial release
www.austriamicrosystems.com/AS8650 revision 1.0 45 - 46 AS8650 datasheet - ordering information 10 ordering information the devices are available as the standard products shown in table 22 . note: all products are rohs compliant and austriamicrosystems green. buy our products or get free samples online at icdirect: http://www.austriamicr osystems.com/icdirect technical support is available at http://www.austriamicrosystems.com/technical-support for further information and requests, please contact us mailto: sales@austriamicrosystems.com or find your local distributor at http://www.austriamicros ystems.com/distributor table 22. ordering information 1 1. the AS8650 provides various configuration options during production. for more information, please contact our sales office. ordering code marking description delivery form package AS8650-zqfp-0001 AS8650 AS8650 power management device with high-speed can interface (standard configuration) tape & reel 36-pin qfn (6x6x0.9)
www.austriamicrosystems.com/AS8650 revision 1.0 46 - 46 AS8650 datasheet - copyrights copyrights copyright ? 1997-2010, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registe red ?. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth he rein or regarding the freedom of the described devices from patent infringement. austriamicrosystems ag reserves the right to change specificatio ns and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with austriamic rosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temper ature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of les s than 100 parts the manufacturing flow might show deviations from the st andard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact

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